Recently, an image forming apparatus using an SIMD type processor has been studied. The SIMD type arithmetic processing unit is for executing a single instruction in parallel, and is composed of a plurality of processor elements (PEs). Moreover, the SIMD type processor can be easily arranged to correspond to a change in the system specification change. Furthermore, functions can be easily added to the SIMD type processor just by changing the program. Accordingly, the SIMD type processor has an advantage in that image processing can be performed by high-speed arithmetic processing.
The SIMD type processor is provided with memories corresponding to each processing executed in parallel. The image processing apparatus writes the input or generated image data once in such memories, then reads and transfers the written image data to the SIMD type processor to thereby adjust the operation timing of each image processing.
For example, in Japanese Patent Application Laid-Open (JP-A) No. 10-289306, a memory control unit for adjusting the write and read timing with respect to the memory of the image data is disclosed. According to such a memory control unit, a time lag at the time of write and read of the image data is removed, thereby enabling efficient control of image processing.
According to the above-described construction, however, the timing of write and read with respect to the memory can be adjusted, but the operation of write and read with respect to the memory can not be controlled. Therefore, with conventional image processing apparatus, there is still room for improvement in optimization of write and read processing with respect to the memory in accordance with the image processing, and for efficiency improvement of image processing.